It is well known that SOI based logic circuits show 20-30% higher performance than logic circuits comparably made on bulk-Si. Currently, Si wafers are ion implanted with oxygen such as 10.sup.18 atoms/cm.sup.2 to form a buried oxide region beneath the surface of the Si. The Si wafers are annealed to form a continuous buried oxide layer (BOX) beneath the surface that isolates electrically the top Si layer from the bulk Si below the BOX. The above process for making SOI wafers is known in the art as separation by implantation of oxygen (SIMOX). SOI wafers are then processed to form devices and/or circuits therein.
In the fabrication of CMOS circuits on bulk Si, shallow trench isolation (STI) has been used to provide electrical isolation between devices. A shallow trench is formed, filled with an insulator and then planarized by Chemical Mechanical Polishing (CMP).
In the fabrication of Dynamic Random Access Memories (DRAM), memory cells consisting of a field effect transistor and a capacitor have been used. IBM Corp. has developed the use of a deep trench capacitor for the memory cell such as described in U.S. Pat. No. 4,688,063 which issued Aug. 18, 1987 by Lu et al. entitled "Dynamic Ram Cell With MOS Trench Capacitor In CMOS." A deep trench is formed and then the sidewalls and bottom are oxidized or coated with an insulator followed by filling the trench with a conductor such as doped poly silicon.